PIC16C63A/65B/73B/74B
TABLE 11-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(2)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
RCREG USART Receive register
0000 0000 0000 0000
(1)
(2)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator register
Legend: u= unchanged, x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
FIGURE 11-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.
2000 Microchip Technology Inc.
DS30605C-page 75
MICROCHIP [ MICROCHIP ]
