PIC16C63A/65B/73B/74B
FIGURE 3-1:
PIC16C63A/65B/73B/74B BLOCK DIAGRAM
13
8
PORTA
PORTB
Data Bus
Program Counter
RA0/AN0(2)
RA1/AN1(2)
RA2/AN2(2)
RA3/AN3/VREF
RA4/T0CKI
EPROM
Program
Memory
(2)
RAM
File
Registers
8 Level Stack
(13-bit)
RA5/SS/AN4(2)
Program
Bus
14
RAM Addr(1)
9
Addr MUX
RB0/INT
RB7:RB1
Instruction reg
Indirect
Addr
7
Direct Addr
8
FSR reg
PORTC
STATUS reg
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
3
MUX
Power-up
Timer
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
PORTD(3)
8
Timing
Generation
Watchdog
Timer
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
Parallel Slave Port
(3)
PORTE(3)
MCLR VDD, VSS
RE0/RD/AN5(2,3)
RE1/WR/AN6(2,3)
RE2/CS/AN7(2,3)
Timer0
CCP1
Timer1
CCP2
Timer2
A/D(2)
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: A/D is not available on the PIC16C63A/65B.
3: PSP and Ports D and E are not available on PIC16C63A/73B.
DS30605C-page 10
2000 Microchip Technology Inc.