PIC16C63A/65B/73B/74B
TABLE 4-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
(3)
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF
(4)
TMR0
PCL
(4)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
IRP
(2)
RP1
(2)
RP0
TO
PD
Z
DC
C
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
STATUS
(4)
FSR
(4)
PORTA
PORTB
PORTC
PORTD
(5)
PORTE
(5)
PCLATH
(1,4)
INTCON
(4)
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
(6)
ADCON0
(6)
Indirect data memory address pointer
—
—
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
—
—
GIE
PSPIF
(5)
—
—
—
PEIE
ADIF
(6)
—
—
—
T0IE
RCIF
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Write Buffer for the upper 5 bits of the Program Counter
INTE
TXIF
–
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
TMR1IF
CCP2IF
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000 --uu uuuu
0000 0000 0000 0000
Timer2 module’s register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
—
SPEN
—
RX9
CCP1X
SREN
CCP1Y
CREN
CCP1M3
—
CCP1M2
FERR
CCP1M1
OERR
CCP1M0
--00 0000 --00 0000
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
USART Transmit Data register
USART Receive Data register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
A/D Result register
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented, read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2:
The IRP and RP1 bits are reserved; always maintain these bits clear.
3:
Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
4:
These registers can be addressed from either bank.
5:
PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6:
The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
2000 Microchip Technology Inc.
DS30605C-page 17
MICROCHIP [ MICROCHIP TECHNOLOGY ]
