PIC16C62B/72A
5.2
Timer1 Oscillator
5.3
Timer1 Interrupt
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). When the
Timer1 oscillator is enabled, RC0 and RC1 pins
become T1OSO and T1OSI inputs, overriding
TRISC<1:0>.
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled by setting TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
The oscillator is a low power oscillator rated up to 200
kHz. It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 5-1 shows the
capacitor selection for the Timer1 oscillator.
5.4
Resetting Timer1 using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TABLE 5-1
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
TABLE 5-2
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
resets
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
-0-- 0000 -0-- 0000
-0-- 0000 -0-- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0Bh,8Bh INTCON GIE
PEIE
ADIF
ADIE
T0IE
—
INTE
—
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0Ch
8Ch
0Eh
0Fh
10h
PIR1
—
—
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
PIE1
—
—
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 29
MICROCHIP [ MICROCHIP ]
