PIC16C62B/72A
2.2.2.1
STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, the write to these three bits is dis-
abled. These bits are set or cleared according to the
device logic. The TO and PD bits are not writable. The
result of an instruction with the STATUS register as
destination may be different than intended.
For example,
CLRF STATUS
will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as
000u u1uu
(where
u
= unchanged).
It is recommended, therefore, that only
BCF, BSF,
SWAPF
and
MOVWF
instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
Note 1:
The IRP and RP1 bits are reserved. Main-
tain these bits clear to ensure upward
compatibility with future products.
Note 2:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the
SUBLW
and
SUBWF
instructions.
REGISTER 2-1:
R/W-0
IRP
bit7
R/W-0
RP1
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
IRP:
Register Bank Select bit (used for indirect addressing)
(reserved, maintain clear)
bit 6-5:
RP1:RP0:
Register Bank Select bits (used for direct addressing)
01
= Bank 1 (80h - FFh)
00
= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
Note:
RP1 is reserved, maintain clear
bit 4:
TO:
Time-out bit
1
= After power-up,
CLRWDT
instruction, or
SLEEP
instruction
0
= A WDT time-out occurred
PD:
Power-down bit
1
= After power-up or by the
CLRWDT
instruction
0
= By execution of the
SLEEP
instruction
Z:
Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
DC:
Digit carry/borrow bit (ADDWF,
ADDLW,SUBLW,SUBWF
instructions) (for borrow, the polarity is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
C:
Carry/borrow bit (ADDWF,
ADDLW,SUBLW,SUBWF
instructions) (for borrow, the polarity is reversed)
1
= A carry-out from the most significant bit of the result occurred
0
= No carry-out from the most significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF,
RLF)
instructions, this bit is loaded with either the high or low order bit of
the source register.
bit 3:
bit 2:
bit 1:
bit 0:
©
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 11
MICROCHIP [ MICROCHIP TECHNOLOGY ]
