PIC16C505
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
4.0
MEMORY ORGANIZATION
PIC16C505 memory is organized into program mem-
ory and data memory. For the PIC16C505, a paging
scheme is used. Program memory pages are accessed
using one STATUS register bit. Data memory banks
are accessed using the File Select Register (FSR).
PIC16C505
PC<11:0>
12
CALL, RETLW
Stack Level 1
Stack Level 2
4.1
Program Memory Organization
The PIC16C505 devices have a 12-bit Program
Counter (PC).
Reset Vector (note 1)
0000h
The 1K x 12 (0000h-03FFh) for the PIC16C505 are
physically implemented. Refer to Figure 4-1.
Accessing a location above this boundary will cause a
wrap-around within the first 1K x 12 space. The
effective reset vector is at 0000h, (see Figure 4-1).
Location 03FFh contains the internal clock oscillator
calibration value. This value should never be
overwritten.
01FFh
0200h
On-chip Program
Memory
1024 Words
03FFh
0400h
7FFh
Note 1: Address 0000h becomes the
effective reset vector. Location
03FFh contains the MOVLW XX
INTERNAL RC oscillator calibration
value.
1998 Microchip Technology Inc.
Preliminary
DS40192B-page 11
MICROCHIP [ MICROCHIP ]
