PIC14000
TABLE 3-1:
Pin Name
CDAC
RA0/AN0
RA1/AN1
PIN DESCRIPTIONS
Pin
No.
22
2
1
I/O
O
I/O
I/O
Pin Type
Input Output
—
AN/ST
AN/ST
AN
CMOS
CMOS
Description
A/D ramp current source output. Normally connected to
external capacitor to generate a linear voltage ramp.
Analog input channel 0. This pin can also serve as a
general-purpose I/O.
Analog input channel 1. This pin can connect to a level
shift network. If enabled, a +0.5V offset is added to the
input voltage. This pin can also serve as a general-
purpose I/O.
Analog input channel 2. This pin can also serve as a
general purpose digital I/O.
Analog input channel 3. This pin can also serve as a gen-
eral purpose digital I/O.
AN1 summing junction output. This pin can be connected
to an external capacitor for averaging small duration
pulses.
LED direct-drive output or programmable reference A out-
put. This pin can also serve as a GPIO. If enabled, this
pin has a weak internal pull-up to V
DD
.
LED direct-drive output or comparator A output. This pin
can also serve as a GPIO. If enabled, this pin has a weak
internal pull-up to V
DD
.
LED direct-drive output. This pin can also serve as a
GPIO. If enabled, this pin has a weak internal pull-up to
V
DD
LED direct-drive output. This pin can also serve as a
GPIO, or an external clock input for Timer0. If enabled,
this pin has a weak internal pull-up to V
DD
.
LED direct-drive output. This pin can also serve as a
GPIO. If enabled, a change on this pin can cause a CPU
interrupt. If enabled, this pin has a weak internal pull-up
to V
DD
.
LED direct-drive output. This pin can also serve as a
GPIO. If enabled, a change on this pin can cause a CPU
interrupt. If enabled, this pin has a weak internal pull-up
to V
DD
.
General purpose I/O. If enabled, is multiplexed as
synchronous serial clock for I
2
C interface. Also is the
serial programming clock. If enabled, a change on this pin
can cause a CPU interrupt. This pin has an N-channel
pull-up device which is disabled in I
2
C mode.
General purpose I/O. If enabled, is multiplexed as
synchronous serial data I/O for I
2
C interface. Also is the
serial programming data line. If enabled, a change on this
pin can cause a CPU interrupt. This pin has an N-channel
pull-up device which is disabled in I
2
C mode.
General purpose I/O. If enabled, is multiplexed as
synchronous serial clock for I
2
C interface. This pin has an
N-channel pull-up device which is disabled in I
2
C mode.
General purpose I/O. If enabled, is multiplexed as
synchronous serial data I/O for I
2
C interface. This pin has
an N-channel pull-up device which is disabled in I
2
C
mode.
General purpose I/O or comparator B output.
RA2/AN2
RA3/AN3
SUM
28
27
21
I/O
I/O
O
AN/ST
AN/ST
—
CMOS
CMOS
AN
RC0/REFA
19
I/O-PU
ST
CMOS
RC1/CMPA
18
I/O-PU
ST
CMOS
RC2
17
I/O-PU
ST
CMOS
RC3/T0CKI
16
I/O-PU
ST
CMOS
RC4
15
I/O-PU
ST
CMOS
RC5
13
I/O-PU
ST
CMOS
RC6/SCLA
12
I/O
ST/SM
NPU/OD
(No P-diode)
RC7/SDAA
11
I/O
ST/SM
NPU/OD
(No P-diode)
RD0/SCLB
6
I/O
ST/SM
NPU/OD
(No P-diode)
NPU/OD
(No P-diode)
RD1/SDAB
5
I/O
ST/SM
RD2/CMPB
4
I/O-PU
AN/ST
CMOS
©
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
