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PIC14000-04/SS 参数 Datasheet PDF下载

PIC14000-04/SS图片预览
型号: PIC14000-04/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28引脚可编程的混合信号控制器 [28-Pin Programmable Mixed Signal Controller]
分类和应用: 微控制器和处理器外围集成电路光电二极管可编程只读存储器时钟
文件页数/大小: 152 页 / 943 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC14000  
4.2.2  
SPECIAL FUNCTION REGISTERS  
The special registers are classified into two sets.  
Special registers associated with the “core” functions  
are described in this section. Those registers related to  
the operation of the peripheral features are described  
in the section specific to that peripheral.  
The special function registers are registers used by the  
CPU and peripheral functions for controlling the  
desired operation of the device (Table 4-3). These reg-  
isters are static RAM.  
TABLE 4-3:  
SPECIAL FUNCTION REGISTERS FOR THE PIC14000  
Address  
Bank0  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
INDF  
(Indirect  
Address)  
Addressing this location uses contents of the FSR to address data memory (not a physical  
register).  
00h*  
01h  
02h*  
03h*  
04h*  
05h  
06h  
07h  
08h  
09h  
0Ah*  
0Bh*  
0Ch  
0Dh  
0Eh  
0Fh  
10h  
11h  
12h  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
TMR0  
Timer0 data  
PCL  
Program Counter’s (PC’s) least significant byte  
STATUS  
FSR  
IRP  
RP1  
RP0  
TO  
PD  
Z
DC  
C
Indirect data memory address pointer  
PORTA data latch.  
PORTA  
Reserved  
PORTC  
PORTD  
Reserved  
PCLATH  
INTCON  
PIR1  
Reserved for emulation.  
PORTC data latch  
PORTD data latch  
Buffered register for the upper 5 bits of the Program Counter (PC)  
GIE  
PEIE  
T0IE  
r
r
T0IF  
r
r
2
CMIF  
PBIF  
I CIF  
RCIF  
ADCIF  
OVFIF  
Reserved  
ADTMRL  
ADTMRH  
Reserved  
Reserved  
Reserved  
A/D capture timer data least significant byte  
A/D capture timer data most significant byte  
2
2
I CBUF  
I C Serial Port Receive Buffer/Transmit Register  
2
2
2
2
2
2
2
I CCON  
WCOL  
I COV  
I CEN  
CKP  
I CM3  
I CM2  
I CM1  
I CM0  
ADCAPL  
ADCAPH  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
ADCON0  
A/D capture latch least significant byte  
A/D capture latch most significant byte  
1Fh  
ADCS3  
ADCS2  
ADCS1  
ADCS0  
AMUXOE  
ADRST ADZERO  
Legend  
— = unimplemented bits, read as ‘0’ but cannot be overwritten  
= reserved bits, default is POR value and should not be overwritten with any value  
r
Reserved indicates reserved register and should not be overwritten with any value  
* indicates registers that can be addressed from either bank  
1996 Microchip Technology Inc.  
Preliminary  
DS40122B-page 15