PIC12F635/PIC16F636/639
8-Pin Diagrams (PDIP, SOIC, DFN, DFN-S)
PDIP, SOIC
V
DD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/V
PP
1
PIC12F635
2
3
4
8
7
6
5
V
SS
GP0/C1IN+/ICSPDAT/ULPWU
GP1/C1IN-/ICSPCLK
GP2/T0CKI/INT/C1OUT
DFN, DFN-S
V
DD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/V
DD
1
2
3
4
8
7
6
5
V
SS
GP0/CIN+/ICSPDAT/ULPWU
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
TABLE 1:
I/O
GP0
GP1
GP2
GP3
GP4
GP5
—
—
Note 1:
2:
Pin
7
6
5
4
3
2
1
8
8-PIN SUMMARY
(PDIP, SOIC, DFN, DFN-S)
Comparators
C1IN+
C1IN-
C1OUT
—
—
—
—
—
Timer
—
—
T0CKI
—
T1G
T1CKI
—
—
Interrupts
IOC
IOC
INT/IOC
IOC
IOC
IOC
—
—
Pull-ups
Y
Y
Y
Y
(2)
Y
Y
—
—
Basic
ICSPDAT/ULPWU
ICSPCLK
—
MCLR/V
PP
OSC2/CLKOUT
OSC1/CLKIN
V
DD
V
SS
Input only.
Only when pin is configured for external MCLR.
©
2007 Microchip Technology Inc.
PIC12F635
DS41232D-page 3