PIC12F635/PIC16F636/639
TABLE 2-1:
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
POR/BOR/
WUR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx
32,137
01h
02h
03h
04h
05h
06h
07h
08h
09h
TMR0
PCL
STATUS
FSR
GPIO
—
Timer0 Module Register
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xx00
—
61,137
32,137
26,137
32,137
47,137
—
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
GP5
GP4
GP3
GP2
GP1
GP0
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
0Ah PCLATH
0Bh INTCON
0Ch PIR1
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000
0000 000x
000- 00-0
—
32,137
28,137
30,137
—
GIE
PEIE
T0IE
CRIF
INTE
—
RAIE
C1IF
T0IF
INTF
—
RAIF(2)
EEIF
LVDIF
OSFIF
TMR1IF
0Dh
—
Unimplemented
0Eh TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1
Holding Register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx
xxxx xxxx
64,137
64,137
0Fh
TMR1H
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
T1CON
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS
TMR1ON
0000 0000
68,137
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WDTCON
CMCON0
—
—
—
—
COUT
—
—
—
—
WDTPS3
CINV
—
WDTPS2
CIS
WDTPS1 WDTPS0
SWDTEN
CM0
---0 1000
144,137
79,137
82,137
—
CM2
—
CM1
-0-0 0000
1Ah CMCON1
—
T1GSS
CMSYNC
---- --10
1Bh
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
1Ch
—
1Dh
—
1Eh
—
1Fh
—
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1:
2:
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mis-
match exists.
© 2007 Microchip Technology Inc.
DS41232D-page 21