PIC12F629/675
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Value on
POR,
Value on all
other
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOD
Resets
05h
GPIO
INTCON
—
GIE
—
—
PEIE
COUT
INTEDG
—
GP5
T0IE
—
GP4
INTE
CINV
T0SE
GP3
GPIE
CIS
GP2
T0IF
CM2
PS2
GP1
INTF
CM1
PS1
GP0
GPIF
CM0
PS0
--xx xxxx
0000 0000
-0-0 0000
1111 1111
--uu uuuu
0000 000u
-0-0 0000
1111 1111
--11 1111
--11 -111
--00 0000
-000 1111
0Bh/8Bh
19h
CMCON
OPTION_REG
TRISIO
WPU
81h
GPPU
—
T0CS
PSA
85h
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111
95h
—
—
WPU5
IOC5
WPU4
IOC4
—
WPU2
IOC2
WPU1
IOC1
WPU0
IOC0
--11 -111
--00 0000
-000 1111
96h
IOC
—
—
IOC3
ANS3
9Fh
ANSEL
—
ADCS2
ADCS1
ADCS0
ANS2
ANS1
ANS0
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.
2010 Microchip Technology Inc.
DS41190G-page 27
MICROCHIP [ MICROCHIP ]
