PIC12F629/675
2.2.2
SPECIAL FUNCTION REGISTERS
FIGURE 2-2:
DATA MEMORY MAP OF
THE PIC12F629/675
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
File
File
Address
Address
(1)
(1)
Indirect addr.
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
OPTION_REG
PCL
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
PCL
STATUS
FSR
STATUS
FSR
GPIO
TRISIO
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
PCON
OSCCAL
WPU
IOC
CMCON
VRCON
EEDATA
EEADR
EECON1
(1)
EECON2
(2)
(2)
(2)
ADRESH
ADCON0
ADRESL
(2)
ANSEL
General
Purpose
Registers
accesses
20h-5Fh
64 Bytes
5Fh
60h
DFh
E0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as ‘0’.
1: Not a physical register.
2: PIC12F675 only.
DS41190G-page 10
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
