PIC12C5XX
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control
the operation of the device (Table 4-1).
TABLE 4-1:
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Value on
All Other
Resets(2)
Value on
Power-On
Reset
Address
Name
TRIS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
--11 1111
--11 1111
N/A
—
—
Contains control bits to configure Timer0, Timer0/WDT
prescaler, wake-up on change, and weak pull-ups
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
N/A
00h
01h
02h
03h
OPTION
INDF
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
TMR0
PCL
(1)
Low order 8 bits of PC
0001 1xxx q00q quuu(3)
STATUS
GPWUF
—
PA0
TO
PD
Z
DC
C
FSR
(PIC12C508/
PIC12C508A/
PIC12C518)
04h
Indirect data memory address pointer
Indirect data memory address pointer
111x xxxx
111u uuuu
FSR
(PIC12C509/
PIC12C509A/
PIC12CR509A/
PIC12CE519)
04h
05h
110x xxxx
0111 ----
11uu uuuu
uuuu ----
OSCCAL
(PIC12C508/
PIC12C509)
CAL3
CAL2
CAL1
CAL0
—
—
—
—
—
—
OSCCAL
(PIC12C508A/
PIC12C509A/
PIC12CE518/
PIC12CE519/
PIC12CR509A)
1000 00--
uuuu uu--
05h
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
--xx xxxx
11xx xxxx
--uu uuuu
11uu uuuu
06h
06h
—
—
GP5
GP5
GP4
GP4
GP3
GP3
GP2
GP2
GP1
GP1
GP0
GP0
GPIO
(PIC12CE518/
PIC12CE519)
SCL
SDA
Legend: Shaded boxes = unimplemented or unused, —= unimplemented, read as ’0’ (if applicable)
x= unknown, u= unchanged, q= see the tables in Section 8.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6
for an explanation of how to access these bits.
2: Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.
3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.
1999 Microchip Technology Inc.
DS40139E-page 15
MICROCHIP [ MICROCHIP ]
