PIC12F629/675
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose regis-
ters and the Special Function registers. The Special
Function registers are located in the first 32 locations of
each bank. Register locations 20h-5Fh are General
Purpose registers, implemented as static RAM and are
mapped across both banks. All other RAM is
unimplemented and returns ‘0’ when read. RP0
(STATUS<5>) is the bank select bit.
2.1
Program Memory Organization
The PIC±2F629/675 devices have a ±3-bit program
counter capable of addressing an 8K x ±4 program
memory space. Only the first ±K x ±4 (0000h - 03FFh)
for the PIC±2F629/675 devices is physically imple-
mented. Accessing a location above these boundaries
will cause a wrap around within the first ±K x ±4 space.
The RESET vector is at 0000h and the interrupt vector
is at 0004h (see Figure 2-±).
• RP0 = 0 Bank 0 is selected
• RP0 = ± Bank ± is selected
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F629/675
Note: The IRP and RP± bits STATUS<7:6> are
reserved and should always be maintained
as ‘0’s.
PC<±2:0>
2.2.1
GENERAL PURPOSE REGISTER
FILE
CALL, RETURN
RETFIE, RETLW
±3
The register file is organized as 64 x 8 in the
PIC±2F629/675 devices. Each register is accessed,
either directly or indirectly, through the File Select
Register FSR (see Section 2.4).
Stack Level ±
Stack Level 2
Stack Level 8
RESET Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
03FFh
0400h
±FFFh
2003 Microchip Technology Inc.
DS41190C-page 7
MICROCHIP [ MICROCHIP ]
