PIC12F629/675
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different RESET
situations as indicated in Table 9-4. These bits are
used in software to determine the nature of the RESET.
See Table 9-7 for a full description of RESET states of
all registers.
9.3
RESET
The PIC±2F629/675 differentiates between various
kinds of RESET:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during SLEEP
d) MCLR Reset during normal operation
e) MCLR Reset during SLEEP
f) Brown-out Detect (BOD)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 9-4.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table ±2-4 in Electrical
Specifications Section for pulse width specification.
Some registers are not affected in any RESET
condition; their status is unknown on POR and
unchanged in any other RESET. Most other registers
are reset to a “RESET state” on:
• Power-on Reset
• MCLR Reset
• WDT Reset
• WDT Reset during SLEEP
• Brown-out Detect (BOD) Reset
FIGURE 9-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP pin
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Detect
S
Q
Q
BODEN
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
R
OSC1/
CLKIN
pin
PWRT
10-bit Ripple Counter
On-chip(1)
RC OSC
Enable PWRT
Enable OST
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the INTOSC/EC oscillator.
2003 Microchip Technology Inc.
DS41190C-page 55
MICROCHIP [ MICROCHIP ]
