PIC12F629/675
FIGURE 3-1:
BLOCK DIAGRAM OF GP0
AND GP1 PINS
3.3
Pin Descriptions and Diagrams
Each GPIO pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D, refer to the
appropriate section in this Data Sheet.
Analog
Input Mode
Data Bus
D
Q
Q
VDD
WR
WPU
CK
Weak
3.3.1
GP0/AN0/CIN+
GPPU
RD
WPU
Figure 3-± shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
VDD
• a general purpose I/O
D
Q
Q
• an analog input for the A/D (PIC±2F675 only)
• an analog input to the comparator
WR
PORT
CK
I/O pin
3.3.2
GP1/AN1/CIN-/VREF
D
Q
Q
Figure 3-± shows the diagram for this pin. The GP± pin
is configurable to function as one of the following:
WR
TRISIO
CK
VSS
Analog
• as a general purpose I/O
Input Mode
RD
TRISIO
• an analog input for the A/D (PIC±2F675 only)
• an analog input to the comparator
RD
PORT
• a voltage reference input for the A/D (PIC±2F675
only)
D
Q
Q
Q
Q
D
CK
WR
IOC
EN
RD
IOC
D
EN
Interrupt-on-Change
RD PORT
To Comparator
To A/D Converter
DS41190C-page 22
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
