PIC12CE5XX
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control
the operation of the device (Table 4-1).
TABLE 4-1:
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Value on
all other
Value on
Power-On
Reset
(2)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
GP1 GP0
Resets
GP5
GP3
GP2
—
—
N/A
TRIS
GP4
--11 1111
--11 1111
Contains control bits to configure Timer0, Timer0/WDT prescaler, wake-
up on change, and weak pull-ups
N/A
00h
01h
OPTION
INDF
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
TMR0
(1)
02h
PCL
Low order 8 bits of PC
1111 1111
0001 1xxx
1111 1111
(3)
—
03h
04h
STATUS
GPWUF
PA0
TO
PD
Z
DC
C
q00q quuu
FSR
(12CE518)
Indirect data memory address pointer
111x xxxx
111u uuuu
FSR
04h
05h
06h
Indirect data memory address pointer
(12CE519)
110x xxxx
1000 00--
11xx xxxx
11uu uuuu
uuuu uu--
11uu uuuu
OSCCAL
GPIO
CAL5
SCL
CAL4 CAL3 CAL2
SDA GP5 GP4
CAL1
GP3
CAL0
GP2
—
—
GP1
GP0
Legend: Shaded boxes = unimplemented or unused, —= unimplemented, read as '0' (if applicable)
x= unknown, u= unchanged, q= see the tables in Section 8.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6
for an explanation of how to access these bits.
Note 2: Other (non-power up) resets include external reset through MCLR, WDT, and wake-up on pin change reset.
Note 3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.
1998 Microchip Technology Inc.
Preliminary
DS40172B-page 13
MICROCHIP [ MICROCHIP ]
