PIC12C5XX
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC
(Program
Counter)
Instruction
Fetch
T0
T0+1
T0+2
NT0
NT0+1
NT0+2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0
NT0+1
T0
Timer0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
TABLE 6-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-On
Reset
Value on
All Other
Resets
Name
TMR0
Bit 7
Timer0 - 8-bit real-time clock/counter
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
GP5 GP4 GP3 GP2 GP1 GP0
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01h
N/A
N/A
xxxx xxxx uuuu uuuu
OPTION
TRIS
—
—
--11 1111 --11 1111
Legend: Shaded cells not used by Timer0, -= unimplemented, x = unknown, u= unchanged,
DS40139E-page 26
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
