PIC12C5XX
5.3
I/O Interfacing
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers are all
set. See Section 7.0 for SCL and SDA description for
PIC12CE5XX.
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output operations.
For input operations these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO,W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O’s to
alternate functions. When acting as alternate functions
the pins will read as ‘0’ during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with wake-up on change. The wake-up on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not enabled.
FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Q
Data
Latch
VDD
WR
Port
CK
P
N
I/O
pin(1,3)
W
Reg
5.2
TRIS Register
D
Q
Q
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see Figure 4-
5.
TRIS
Latch
VSS
TRIS ‘f’
CK
Reset
(2)
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD
and VSS.
Note 2: See Table 3-1 for buffer type.
Note 3: See Section 7.0 for SCL and SDA
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
description for PIC12CE5XX
1999 Microchip Technology Inc.
DS40139E-page 21
MICROCHIP [ MICROCHIP ]
