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PIC12F629-I/SNVAO 参数 Datasheet PDF下载

PIC12F629-I/SNVAO图片预览
型号: PIC12F629-I/SNVAO
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PDSO8]
分类和应用: 闪存微控制器
文件页数/大小: 136 页 / 1422 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F629/675  
When the A/D clock source is something other than  
RC, a SLEEPinstruction causes the present conversion  
to be aborted, and the A/D module is turned off. The  
ADON bit remains set.  
7.3  
A/D Operation During Sleep  
The A/D converter module can operate during Sleep.  
This requires the A/D clock source to be set to the  
internal RC oscillator. When the RC clock source is  
selected, the A/D waits one instruction before starting  
the conversion. This allows the SLEEPinstruction to be  
executed, thus eliminating much of the switching noise  
from the conversion. When the conversion is complete,  
the GO/DONE bit is cleared, and the result is loaded  
into the ADRESH:ADRESL registers. If the A/D  
interrupt is enabled, the device awakens from Sleep. If  
the A/D interrupt is not enabled, the A/D module is  
turned off, although the ADON bit remains set.  
7.4  
Effects of Reset  
A device Reset forces all registers to their Reset state.  
Thus the A/D module is turned off and any pending  
conversion is aborted. The ADRESH:ADRESL  
registers are unchanged.  
TABLE 7-2:  
SUMMARY OF A/D REGISTERS  
Value on  
POR,  
BOD  
Value on  
all other  
Resets  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
05h  
GPIO  
GPIO5  
T0IE  
GPIO4  
INTE  
GPIO3  
GPIE  
CMIF  
GPIO2  
T0IF  
GPIO1  
INTF  
GPIO0 --xx xxxx --uu uuuu  
GPIF 0000 0000 0000 000u  
TMR1IF 00-- 0--0 00-- 0--0  
0Bh, 8Bh INTCON  
GIE  
EEIF  
PEIE  
ADIF  
0Ch  
1Eh  
1Fh  
85h  
8Ch  
9Eh  
9Fh  
PIR1  
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result  
xxxx xxxx uuuu uuuu  
00-- 0000 00-- 0000  
ADCON0  
TRISIO  
PIE1  
ADFM  
VCFG  
CHS1  
CHS0  
GO  
ADON  
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111  
CMIE TMR1IE 00-- 0--0 00-- 0--0  
EEIE  
ADIE  
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result  
ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0  
xxxx xxxx uuuu uuuu  
-000 1111 -000 1111  
Legend: x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for A/D converter module.  
DS41190G-page 48  
2010 Microchip Technology Inc.