PIC12F629/675
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
8.1
EEADR
The EEADR register can address up to a maximum of
128 bytes of data EEPROM. Only seven of the eight
bits in the register (EEADR<6:0>) are required. The
MSb (bit 7) is ignored.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it, and rewrite the
location. The data and address will be cleared,
therefore, the EEDATA and EEADR registers will need
to be re-initialized.
The upper bit should always be ‘0’ to remain upward
compatible with devices that have more data EEPROM
memory.
8.2
EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are non-
implemented and read as ‘0’s.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
REGISTER 8-3:
EECON1: EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
WRERR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal
operation or BOD detect)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the data EEPROM
WR: Write Control bit
1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
be set, not cleared, in software.)
0= Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set, not cleared, in software).
0= Does not initiate an EEPROM read
DS41190G-page 50
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
