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PIC12F629-I/PG 参数 Datasheet PDF下载

PIC12F629-I/PG图片预览
型号: PIC12F629-I/PG
PDF下载: 下载PDF文件 查看货源
内容描述: [8-Pin, Flash-Based 8-Bit CMOS Microcontrollers, -40C to +85C, 8-PDIP, TUBE]
分类和应用: 时钟微控制器光电二极管外围集成电路
文件页数/大小: 128 页 / 1205 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F629/675  
It is recommended, therefore, that only BCF, BSF,  
SWAPF and MOVWF instructions are used to alter the  
STATUS register, because these instructions do not  
affect any STATUS bits. For other instructions not  
affecting any STATUS bits, see the “Instruction Set  
Summary”.  
2.2.2.1  
STATUS Register  
The STATUS register, shown in Register 2-1, contains:  
• the arithmetic status of the ALU  
• the RESET status  
• the bank select bits for data memory (SRAM)  
The STATUS register can be the destination for any  
instruction, like any other register. If the STATUS  
register is the destination for an instruction that affects  
the Z, DC or C bits, then the write to these three bits is  
disabled. These bits are set or cleared according to the  
device logic. Furthermore, the TO and PD bits are not  
writable. Therefore, the result of an instruction with the  
STATUS register as destination may be different than  
intended.  
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not  
used by the PIC12F629/675 and should  
be maintained as clear. Use of these bits  
is not recommended, since this may affect  
upward compatibility with future products.  
2: The C and DC bits operate as a Borrow  
and Digit Borrow out bit, respectively, in  
subtraction. See the SUBLW and SUBWF  
instructions for examples.  
For example, CLRF STATUSwill clear the upper three  
bits and set the Z bit. This leaves the STATUS register  
as 000u u1uu(where u= unchanged).  
REGISTER 2-1:  
STATUS — STATUS REGISTER (ADDRESS: 03h OR 83h)  
Reserved Reserved  
IRP RP1  
bit 7  
R/W-0  
RP0  
R-1  
TO  
R-1  
PD  
R/W-x  
Z
R/W-x  
DC  
R/W-x  
C
bit 0  
bit 7  
bit 6  
bit 5  
IRP: This bit is reserved and should be maintained as ‘0’  
RP1: This bit is reserved and should be maintained as ‘0’  
RP0: Register Bank Select bit (used for direct addressing)  
0= Bank 0 (00h - 7Fh)  
1= Bank 1 (80h - FFh)  
bit 4  
bit 3  
bit 2  
bit 1  
TO: Time-out bit  
1= After power-up, CLRWDTinstruction, or SLEEPinstruction  
0= A WDT time-out occurred  
PD: Power-down bit  
1= After power-up or by the CLRWDTinstruction  
0= By execution of the SLEEPinstruction  
Z: Zero bit  
1= The result of an arithmetic or logic operation is zero  
0= The result of an arithmetic or logic operation is not zero  
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)  
For borrow, the polarity is reversed.  
1= A carry-out from the 4th low order bit of the result occurred  
0= No carry-out from the 4th low order bit of the result  
bit 0  
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)  
1= A carry-out from the Most Significant bit of the result occurred  
0= No carry-out from the Most Significant bit of the result occurred  
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s  
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is  
loaded with either the high or low order bit of the source register.  
Legend:  
R = Readable bit  
W = Writable bit  
’1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
’0’ = Bit is cleared x = Bit is unknown  
- n = Value at POR  
© 2007 Microchip Technology Inc.  
DS41190E-page 11