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PIC10F200-I/P 参数 Datasheet PDF下载

PIC10F200-I/P图片预览
型号: PIC10F200-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 6引脚8位闪存微控制器 [6-Pin, 8-Bit Flash Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 96 页 / 1447 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC10F200/202/204/206  
CLRW  
Clear W  
BTFSS  
Bit Test f, Skip if Set  
Syntax:  
[ label ] CLRW  
None  
Syntax:  
[ label ] BTFSS f,b  
Operands:  
Operation:  
Operands:  
0 f 31  
0 b < 7  
00h (W);  
1 Z  
Operation:  
skip if (f<b>) = 1  
Status Affected:  
Description:  
Z
Status Affected: None  
The W register is cleared. Zero bit  
(Z) is set.  
Description:  
If bit ‘b’ in register ‘f’ is ‘1’, then the  
next instruction is skipped.  
If bit ‘b’ is ‘1’, then the next instruc-  
tion fetched during the current  
instruction execution, is discarded  
and a NOPis executed instead,  
making this a two-cycle instruction.  
CLRWDT  
Syntax:  
Clear Watchdog Timer  
[ label ] CLRWDT  
None  
CALL  
Subroutine Call  
[ label ] CALL k  
0 k 255  
Syntax:  
Operands:  
Operation:  
Operands:  
Operation:  
00h WDT;  
0 WDT prescaler (if assigned);  
(PC) + 1Top-of-Stack;  
k PC<7:0>;  
1 TO;  
1 PD  
(STATUS<6:5>) PC<10:9>;  
0 PC<8>  
Status Affected: TO, PD  
Status Affected: None  
Description:  
The CLRWDTinstruction resets the  
Description:  
Subroutine call. First, return  
WDT. It also resets the prescaler, if  
the prescaler is assigned to the  
WDT and not Timer0. Status bits  
TO and PD are set.  
address (PC + 1) is PUSHed onto  
the stack. The eight-bit immediate  
address is loaded into PC  
bits <7:0>. The upper bits  
PC<10:9> are loaded from  
STATUS<6:5>, PC<8> is cleared.  
CALLis a two-cycle instruction.  
CLRF  
Clear f  
COMF  
Complement f  
Syntax:  
[ label ] CLRF  
0 f 31  
f
Syntax:  
Operands:  
[ label ] COMF f,d  
Operands:  
Operation:  
0 f 31  
d [0,1]  
00h (f);  
1 Z  
Operation:  
(f) (dest)  
Status Affected:  
Description:  
Z
Status Affected:  
Description:  
Z
The contents of register ‘f’ are  
cleared and the Z bit is set.  
The contents of register ‘f’ are  
complemented. If ‘d’ is ‘0’, the  
result is stored in the W register. If  
‘d’ is ‘1’, the result is stored back in  
register ‘f’.  
DS41239D-page 54  
© 2007 Microchip Technology Inc.  
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