PIC10F200/202/204/206
5.3
I/O Interfacing
5.0
I/O PORT
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input-
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP<3:0>). Bits 7 through 4 are unimple-
mented and read as ‘0’s. Please note that GP3 is an
input-only pin. Pins GP0, GP1 and GP3 can be config-
ured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not pin selectable. If GP3/MCLR is config-
ured as MCLR, weak pull-up is always on and wake-up
on change for this pin is not enabled.
FIGURE 5-1:
PIC10F200/202/204/206
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Q
Data
Latch
VDD
P
VDD
WR
Port
5.2
TRIS Registers
CK
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS
f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are GP3, which is input-only and the GP2/T0CKI/
COUT/FOSC4 pin, which may be controlled by various
registers. See Table 5-1.
N
I/O
pin
W
Reg
D
Q
Q
TRIS
Latch
VSS VSS
TRIS‘f’
CK
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Reset
(1)
RD Port
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
Note 1: See Table 3-2 for buffer type.
TABLE 5-1:
ORDER OF PRECEDENCE
FOR PIN FUNCTIONS
Priority
GP0
CIN+
GP1
GP2
GP3
1
2
3
4
CIN-
FOSC4
COUT
I/MCLR
TRIS GPIO TRIS GPIO
—
—
—
—
—
—
—
T0CKI
TRIS GPIO
© 2007 Microchip Technology Inc.
DS41239D-page 25
MICROCHIP [ MICROCHIP ]
