PIC10F200/202/204/206
12.3 DC Characteristics: PIC10F200/202/204/206 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC specification
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
VIL Input Low Voltage
I/O ports:
D030
D030A
D031
with TTL buffer
Vss
Vss
Vss
—
—
—
0.8
V
V
V
For all 4.5 ≤ VDD ≤ 5.5V
0.15 VDD
0.2 VDD
Otherwise
with Schmitt Trigger
buffer
D032
MCLR, T0CKI
Vss
—
0.2 VDD
V
VIH Input High Voltage
I/O ports:
—
—
—
—
D040
D040A
D041
with TTL buffer
2.0
VDD
VDD
VDD
V
V
V
4.5 ≤ VDD ≤ 5.5V
Otherwise
0.25 VDD + 0.8
0.8VDD
with Schmitt Trigger
For entire VDD range
buffer
D042
D070
MCLR, T0CKI
0.8VDD
50
—
VDD
400
V
(3)
IPUR GPIO weak pull-up current
250
μA VDD = 5V, VPIN = VSS
(1, 2)
IIL
Input Leakage Current
D060
D061
I/O ports
—
—
±0.1
±0.7
± 1
± 5
μA Vss ≤ VPIN ≤ VDD, Pin at high-imped-
ance
(4)
GP3/MCLR
μA Vss ≤ VPIN ≤ VDD
Output Low Voltage
D080
I/O ports
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V, -40°C to
+85°C
D080A
IOL = 7.0 mA, VDD = 4.5V, -40°C to
+125°C
Output High Voltage
(2)
D090
I/O ports
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V, -40°C to
+85°C
D090A
IOH = -2.5 mA, VDD = 4.5V, -40°C to
+125°C
Capacitive Loading Specs on Output Pins
All I/O pins
D101
—
—
50*
pF
†
*
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as coming out of the pin.
3: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the
MCLR circuit is higher than the standard I/O logic.
© 2007 Microchip Technology Inc.
DS41239D-page 67
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