PIC10F200/202/204/206
FIGURE 3-2:
PIC10F204/206 BLOCK DIAGRAM
9-10
8
GPIO
Data Bus
Program Counter
Flash
512 x12 or
256 x12
Program
Memory
GP0/ICSPDAT/CIN+
GP1/ICSPCLK/CIN-
GP2/T0CKI/COUT/FOSC4
GP3/MCLR/VPP
RAM
24 or 16
bytes
Stack 1
Stack 2
File
Registers
Program
Bus
12
RAM Addr
9
Addr MUX
Instruction Reg
Indirect
Addr
5
Direct Addr
5-7
FSR Reg
STATUS Reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
Power-on
Reset
ALU
8
Watchdog
Timer
Timing
Generation
W Reg
Internal RC
Clock
CIN+
CIN-
Timer0
Comparator
MCLR
VDD, VSS
COUT
© 2007 Microchip Technology Inc.
DS41239D-page 11
MICROCHIP [ MICROCHIP ]
