MCP6541/1R/1U/2/3/4
the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
4.0
APPLICATIONS INFORMATION
The MCP6541/2/3/4 family of push-pull output compar-
ators are fabricated on Microchip’s state-of-the-art
CMOS process. They are suitable for a wide range of
applications requiring very low power consumption.
pin (VIN+ and VIN–) from going too far above VDD
.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
VDD
4.1
Comparator Inputs
4.1.1
PHASE REVERSAL
D1
The MCP6541/1R/1U/2/3/4 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
+
V1
R1
VOUT
MCP6G0X
–
D2
V2
R2
R3
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
VSS – (minimum expected V1)
2 mA
R1 ≥
R2 ≥
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to pro-
tect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
VSS – (minimum expected V2)
2 mA
FIGURE 4-2:
Protecting the Analog Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
Bond
VDD
Pad
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-37. Applications that are
high impedance may need to limit the useable voltage
range.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
4.1.3
NORMAL OPERATION
Bond
Pad
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages. With
this topology, the input voltage is 0.3V above VDD and
0.3V below VSS. Therefore, the input offset voltage is
measured at both VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
VSS
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
The MCP6541/1R/1U/2/3/4 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV) and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage (200 µVp-p). Figure 4-3 depicts this behavior.
DS21696E-page 14
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
