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MCP4551T-103E/MS 参数 Datasheet PDF下载

MCP4551T-103E/MS图片预览
型号: MCP4551T-103E/MS
PDF下载: 下载PDF文件 查看货源
内容描述: 7/8位单/双I2C数字电位器具有易失性存储器 [7/8-Bit Single/Dual I2C Digital POT with Volatile Memory]
分类和应用: 转换器电位器数字电位计存储光电二极管PC
文件页数/大小: 88 页 / 2308 K
品牌: MICROCHIP [ MICROCHIP ]
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MCP453X/455X/463X/465X  
2
TABLE 1-2:  
I C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)  
I2C AC Characteristics  
Standard Operating Conditions (unless otherwise specified)  
Operating Temperature –40°C TA +125°C (Extended)  
Operating Voltage VDD range is described in AC/DC characteristics  
Param.  
No.  
Sym  
Characteristic  
Min  
Max Units  
Conditions  
107  
TSU:DAT Data input setup 100 kHz mode  
250  
100  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Note 2  
Note 1  
time  
400 kHz mode  
1.7 MHz mode  
3.4 MHz mode  
109  
TAA  
Output valid  
from clock  
100 kHz mode  
400 kHz mode  
1.7 MHz mode  
3450  
900  
150  
Cb = 100 pF,  
Note 1, Note 7  
310  
ns  
Cb = 400 pF,  
Note 1, Note 5  
3.4 MHz mode  
100 kHz mode  
400 kHz mode  
1.7 MHz mode  
3.4 MHz mode  
4700  
1300  
N.A.  
N.A.  
150  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Cb = 100 pF, Note 1  
110  
TBUF  
Bus free time  
Time the bus must be free  
before a new transmission  
can start  
TSP  
Input filter spike 100 kHz mode  
50  
50  
10  
10  
Philips Spec states N.A.  
suppression  
(SDA and SCL)  
400 kHz mode  
1.7 MHz mode  
Spike suppression  
Spike suppression  
3.4 MHz mode  
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region  
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.  
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the  
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not  
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,  
it must output the next data bit to the SDA line  
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before  
the SCL line is released.  
3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH  
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but  
must be tested in order to ensure that the output data will meet the setup and hold specifications for the  
receiving device.  
4: Use Cb in pF for the calculations.  
5: Not Tested  
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do  
not unintentionally create a Start or Stop condition.  
7: Ensured by the TAA 3.4 MHz specification test.  
DS22096A-page 16  
© 2008 Microchip Technology Inc.