MCP41XXX/42XXX
5.8
Using the MCP41XXX/42XXX in
SPI Mode 1,1
It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
Data is always latched in
on the rising edge of SCK.
Data is always clocked out the SO
pin after the falling edge of SCK.
Data Registers are
loaded on rising
CS†
edge of CS. Shift
register is loaded
with zeros at this time.
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
SCK
COMMAND BYTE
DATA BYTE
Don’t
Don’t
Care
Bits
Channel
Select
Bits
Care
Bits
Command
Bits
New Register Data
X
X
P1*
P0
X
C0
X
D7 D6 D5 D4 D3 D2 D1 D0
C1
SI
SO pin will always
drive low when CS
goes high.
First 16 bits Shifted out will always be zeros
X
SO‡
†
There must always be multiples of 16 clocks while CS is low or commands will abort.
The serial data out pin (SO) is only available on the MCP42XXX device.
‡
FIGURE 5-5:
Timing Diagram for SPI Mode 1,1 Operation.
DS11195C-page 22
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
