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MCP41010-I/SN 参数 Datasheet PDF下载

MCP41010-I/SN图片预览
型号: MCP41010-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 单/双通道数字电位SPI⑩接口 [Single/Dual Digital Potentiometer with SPI⑩ Interface]
分类和应用: 转换器数字电位计电阻器光电二极管PC
文件页数/大小: 33 页 / 682 K
品牌: MICROCHIP [ MICROCHIP ]
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MCP41XXX/42XXX  
3.9  
Shutdown (SHDN)  
3.0  
PIN DESCRIPTIONS  
(MCP42XXX devices only)  
3.1  
PA0, PA1  
The Shutdown pin has a Schmitt Trigger input. Pulling  
this pin low will put the device in a power-saving mode  
where A terminal is opened and the B and W terminals  
are connected for all potentiometers. This pin should  
not be toggled low when the CS pin is low. In order to  
minimize power consumption, this pin has an active  
pull-up circuit. The performance of this circuit is shown  
in Figure 2-12. This pin will draw negligible current at  
logic level ‘0’ and logic level ‘1’. Do not leave this pin  
floating.  
Potentiometer Terminal A Connection.  
3.2  
PB0, PB1  
Potentiometer Terminal B Connection.  
3.3  
PW0, PW1  
Potentiometer Wiper Connection.  
3.4  
Chip Select (CS)  
TABLE 3-1:  
Pin # Name  
MCP41XXX Pins  
Function  
This is the SPI port chip select pin and is used to exe-  
cute a new command after it has been loaded into the  
shift register. This pin has a Schmitt Trigger input.  
1
2
3
4
5
6
7
8
CS Chip Select  
SCK Serial Clock  
SI Serial Data Input  
3.5  
Serial Clock (SCK)  
This is the SPI port clock pin and is used to clock-in  
new register data. Data is clocked into the SI pin on the  
rising edge of the clock and out the SO pin on the falling  
edge of the clock. This pin is gated to the CS pin (i.e.,  
the device will not draw any more current if the SCK pin  
is toggling when the CS pin is high). This pin has a  
Schmitt Trigger input.  
VSS Ground  
PA0 Terminal A Connection For Pot 0  
PW0 Wiper Connection For Pot 0  
PB0 Terminal B Connection For Pot 0  
VDD Power  
3.6  
Serial Data Input (SI)  
TABLE 3-2:  
Pin # Name  
MCP42XXX Pins  
Function  
This is the SPI port serial data input pin. The command  
and data bytes are clocked into the shift register using  
this pin. This pin is gated to the CS pin (i.e., the device  
will not draw any more current if the SI pin is toggling  
when the CS pin is high). This pin has a Schmitt Trigger  
input.  
1
2
CS Chip Select  
SCK Serial Clock  
SI Serial Data Input  
3
4
VSS Ground  
3.7  
Serial Data Output (SO)  
5
PB1 Terminal B Connection For Pot 1  
PW1 Wiper Connection For Pot 1  
PA1 Terminal A Connection For Pot 1  
PA0 Terminal A Connection For Pot 0  
PW0 Wiper Connection For Pot 0  
PB0 Terminal B Connection For Pot 0  
RS Reset Input  
(MCP42XXX devices only)  
6
This is the SPI port serial data output pin used for  
daisy-chaining more than one device. Data is clocked  
out of the SO pin on the falling edge of clock. This is a  
push-pull output and does not go to a high-impedance  
state when CS is high. It will drive a logic-low when CS  
is high.  
7
8
9
10  
11  
12  
13  
14  
3.8  
Reset (RS)  
SHDN Shutdown Input  
(MCP42XXX devices only)  
SO Data Out for Daisy-Chaining  
VDD Power  
The Reset pin will set all potentiometers to mid-scale  
(Code 80h) if this pin is brought low for at least 150 ns.  
This pin should not be toggled low when the CS pin is  
low. It is possible to toggle this pin when the SHDN pin  
is low. In order to minimize power consumption, this pin  
has an active pull-up circuit. The performance of this  
circuit is shown in Figure 2-12. This pin will draw negli-  
gible current at logic level ‘0’ and logic level ‘1’. Do not  
leave this pin floating.  
DS11195C-page 12  
2003 Microchip Technology Inc.