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MCP4132-502E/MS 参数 Datasheet PDF下载

MCP4132-502E/MS图片预览
型号: MCP4132-502E/MS
PDF下载: 下载PDF文件 查看货源
内容描述: 7/8位单/双SPI数字电位器具有易失性存储器 [7/8-Bit Single/Dual SPI Digital POT with Volatile Memory]
分类和应用: 转换器电位器数字电位计存储电阻器光电二极管
文件页数/大小: 88 页 / 2525 K
品牌: MICROCHIP [ MICROCHIP ]
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MCP413X/415X/423X/425X  
3.0  
PIN DESCRIPTIONS  
The descriptions of the pins are listed in Table 3-1.  
Additional descriptions of the device pins follows.  
TABLE 3-1:  
PINOUT DESCRIPTION FOR THE MCP413X/415X/423X/425X  
Pin  
Weak  
Single  
Dual  
Pot  
Pull-up/  
Standard Function  
Buffer  
Type  
Rheo Pot (1) Rheo  
Symbol  
I/O  
down (2)  
8L  
8L  
10L  
14L  
16L  
1
2
1
2
1
2
1
2
16  
1
CS  
I
I
I
HV w/ST “smart” SPI Chip Select Input  
HV w/ST “smart” SPI Clock Input  
SCK  
3
3
3
3
2
SDI  
HV w/ST “smart” SPI Serial Data Input  
SDI/SDO  
I/O HV w/ST “smart” SPI Serial Data Input/Output  
(Note 1, Note 3)  
4
4
5
4
5
4
5
3, 4 VSS  
A
P
No  
No  
No  
No  
No  
No  
Ground  
5
6
P1B  
P1W  
P1A  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Potentiometer 1 Terminal B  
Potentiometer 1 Wiper Terminal  
Potentiometer 1 Terminal A  
Potentiometer 0 Terminal A  
Potentiometer 0 Wiper Terminal  
Potentiometer 0 Terminal B  
6
6
A
7
7
7
A
8
8
P0A  
A
5
6
9
9
P0W  
P0B  
A
6
7
8
10  
12  
13  
14  
11  
10  
13  
14  
15  
A
8
9
SHDN  
SDO  
VDD  
I
HV w/ST “smart” Hardware Shutdown  
7
O
O
P
No  
SPI Serial Data Out  
Positive Power Supply Input  
No Connection  
8
10  
11  
9
11,12 NC  
17 EP  
9
Exposed Pad (Note 4)  
Legend:  
HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)  
A = Analog pins (Potentiometer terminals)  
O = digital output  
I = digital input (high Z)  
I/O = Input / Output  
P = Power  
Note 1: The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin  
(SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been  
requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin.  
2: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and  
shutdown current.  
3: The SDO is an open drain output, which uses the internal “smart” pull-up. The SDI input data rate can be  
at the maximum SPI frequency. the SDO output data rate will be limited by the “speed” of the pull-up,  
customers can increase the rate with external pull-up resistors.  
4: The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively  
connected to the die substrate, and therefore should be unconnected or connected to the same ground as  
the device’s VSS pin.  
© 2008 Microchip Technology Inc.  
DS22060B-page 31