MCP3201
4.2
Reference Input
4.0
DEVICE OPERATION
The reference input (VREF) determines the analog input
voltage range and the LSB size, as shown below.
The MCP3201 A/D Converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the first rising edge of the
serial clock after CS has been pulled low. Following this
sample time, the input switch of the converter opens
and the device uses the collected charge on the
internal sample and hold capacitor to produce a serial
12-bit digital output code. Conversion rates of 100 ksps
are possible on the MCP3201 device. See Section 6.2
“Maintaining Minimum Clock Speed” for information
on minimum clock rates. Communication with the
device is done using a 3-wire SPI-compatible interface.
EQUATION 4-1:
VREF
LSB Size = ------------
4096
As the reference input is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D Converter is a function of the
analog input signal and the reference input as shown
below.
EQUATION 4-2:
4.1
Analog Inputs
4096*VIN
Digital Output Code = ------------------------
VREF
The MCP3201 device provides a single pseudo-differ-
ential input. The IN+ input can range from IN- to VREF
(VREF + IN-). The IN- input is limited to ±100 mV from
the VSS rail. The IN- input can be used to cancel small
signal common-mode noise which is present on both
the IN+ and IN- inputs.
Where:
VIN
=
=
Analog Input Voltage = V(IN+) - V(IN-)
Reference Voltage
VREF
For the A/D Converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough
time to acquire a 12-bit accurate voltage level during
the 1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
When using an external voltage reference device, the
system designer should always refer to the
manufacturer’s recommendations for circuit layout.
Any instability in the operation of the reference device
will have a direct effect on the operation of the
A/D Converter.
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS
)
impedance, directly affecting the time that is required to
charge the capacitor (CSAMPLE). Consequently, a
larger source impedance increases the offset, gain,
and integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational
amplifier such as the MCP601, which has a closed loop
output impedance of tens of ohms. The adverse affects
of higher source impedances are shown in Figure 4-2.
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the
output code will be FFFh. If the voltage level at IN- is
more than 1 LSB below VSS, then the voltage level at
the IN+ input will have to go below VSS to see the 000h
output code. Conversely, if IN- is more than 1 LSB
above VSS, then the FFFh code will not be seen unless
the IN+ input level goes above VREF level.
© 2008 Microchip Technology Inc.
DS21290E-page 17
MICROCHIP [ MICROCHIP ]
