MCP3004/3008
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V,
TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for
VDD = 5V, TAMB = 25°C.
Parameter
Sym
Min
Typ
Max
Units
Conditions
Analog Inputs
Input Voltage Range for CH0 or
CH1 in Single-Ended Mode
VSS
IN-
—
—
—
VREF
V
Input Voltage Range for IN+ in
pseudo-differential mode
VREF+IN-
VSS+100
Input Voltage Range for IN- in
pseudo-differential mode
V
SS-100
mV
Leakage Current
—
—
—
0.001
1000
20
±1
—
—
µA
Ω
Switch Resistance
See Figure 4-1
Sample Capacitor
pF
See Figure 4-1
Digital Input/Output
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Straight Binary
VIH
VIL
0.7 VDD
—
—
—
—
—
—
—
—
0.3 VDD
—
V
V
VOH
VOL
ILI
4.1
—
V
IOH = -1 mA, VDD = 4.5V
IOL = 1 mA, VDD = 4.5V
VIN = VSS or VDD
0.4
V
-10
-10
—
10
µA
µA
pF
ILO
10
VOUT = VSS or VDD
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Pin Capacitance
(All Inputs/Outputs)
CIN,
COUT
10
Timing Parameters
Clock Frequency
fCLK
—
—
3.6
1.35
MHz VDD = 5V (Note 3)
MHz
VDD = 2.7V (Note 3)
Clock High Time
tHI
tLO
125
125
100
—
—
—
—
—
—
—
—
—
—
—
0
ns
Clock Low Time
ns
CS Fall To First Rising CLK Edge
CS Fall To Falling CLK Edge
Data Input Setup Time
Data Input Hold Time
tSUCS
tCSD
tSU
ns
ns
—
50
50
ns
tHD
—
ns
CLK Fall To Output Data Valid
tDO
—
125
200
ns
ns
VDD = 5V, See Figure 1-2
VDD = 2.7V, See Figure 1-2
CLK Fall To Output Enable
tEN
—
—
125
200
ns
ns
VDD = 5V, See Figure 1-2
VDD = 2.7V, See Figure 1-2
CS Rise To Output Disable
CS Disable Time
tDIS
tCSH
tR
—
270
—
—
—
—
100
—
ns
ns
ns
See Test Circuits, Figure 1-2
DOUT Rise Time
100
See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
—
—
100
ns
See Test Circuits, Figure 1-2
(Note 1)
Note 1: This parameter is established by characterization and not 100% tested.
2: See graphs that relate linearity performance to VREF levels.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,
for more information.
© 2007 Microchip Technology Inc.
DS21295C-page 3
MICROCHIP [ MICROCHIP ]
