MCP2210
TABLE 3-18: RESPONSE 1 STRUCTURE (CONTINUED)
Byte
Index
Meaning
14
Last Data Byte to CS (De-asserted) Delay (quanta of 100 µs) – 16-bit value (low byte)
Example: If a 500 µs delay between the last data byte sent and the CS being de-asserted is required,
the value will be 0x0005.
- This byte position will have a value of: 0x05
15
Last Data Byte to CS (De-asserted) Delay (quanta of 100 µs) – 16-bit value (high byte)
Example: If a 500 µs delay between the last data byte sent and the CS being de-asserted is required,
the value will be 0x0005.
- This byte position will have a value of: 0x00
16
17
18
Delay Between Subsequent Data Bytes (quanta of 100 µs) – 16-bit value (low byte)
Example: If a 500 µs delay between two consecutive data bytes is required, the value will be 0x0005.
- This byte position will have a value of: 0x05
Delay Between Subsequent Data Bytes (quanta of 100 µs) – 16-bit value (high byte)
Example: If a 500 µs delay between two consecutive data bytes is required, the value will be 0x0005.
- This byte position will have a value of: 0x00
Bytes to Transfer per SPI Transaction – 16-bit value (low byte)
Example: If an SPI transaction of 1250 bytes long is required, the corresponding hex value
will be 0x04E2.
- This byte position will have a value of: 0xE2
19
20
Bytes to Transfer per SPI Transaction – 16-bit value (high byte)
Example: If an SPI transaction of 1250 bytes long is required, the corresponding hex value
will be 0x04E2
- This byte position will have a value of: 0x04
SPI Mode
• 0x00 – SPI mode 0
• 0x01 – SPI mode 1
• 0x02 – SPI mode 2
• 0x03 – SPI mode 3
21 - 63 Don’t care
FIGURE 3-6:
GET SPI POWER-UP TRANSFER SETTINGS LOGIC FLOW
Get NVRAM SPI
Transfer Settings
Response 1
NVRAM SPI
Transfer Settings
Retrieved
2011 Microchip Technology Inc.
DS22288A-page 25
MICROCHIP [ MICROCHIP ]
