MCP1825/MCP1825S
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
3-Pin Fixed
Output
5-Pin Fixed
Output
Adjustable
Output
Name
Description
—
1
2
1
2
SHDN
VIN
Shutdown Control Input (active-low)
Input Voltage Supply
1
2
3
3
GND
VOUT
PWRGD
ADJ
Ground
3
4
4
Regulated Output Voltage
Power Good Output
—
—
—
5
—
5
Voltage Adjust/Sense Input
Exposed Pad of the Package (ground potential)
Exposed Pad Exposed Pad Exposed Pad
EP
3.1
Shutdown Control Input (SHDN)
3.5
Power Good Output (PWRGD)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 110 µs (typical) from the
time the LDO output is within 92% + 3% (maximum
hysteresis) of the regulated output value on power-up.
This delay time is internally fixed.
3.2
Input Voltage Supply (VIN)
3.6
Output Voltage Adjust Input (ADJ)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.7
Exposed Pad (EP)
3.3
Ground (GND)
The DDPAK and TO-220 package have an exposed
tab on the package. A heat sink may may be mount to
the tab to aid in the removal of heat from the package
during operation. The exposed tab is at the ground
potential of the LDO.
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications that have switching or noisy inputs, tie
the GND pin to the return of the output capacitor.
Ground planes help lower inductance and voltage
spikes caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4
Regulated Output Voltage (VOUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1825/MCP1825S
is stable with ceramic, tantalum and aluminum-electro-
lytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.
DS22056B-page 16
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
