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KSZ8041NLAM-TR 参数 Datasheet PDF下载

KSZ8041NLAM-TR图片预览
型号: KSZ8041NLAM-TR
PDF下载: 下载PDF文件 查看货源
内容描述: [DATACOM, QCC32]
分类和应用:
文件页数/大小: 45 页 / 584 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第6页浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第7页浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第8页浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第9页浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第11页浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第12页浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第13页浏览型号KSZ8041NLAM-TR的Datasheet PDF文件第14页  
Micrel, Inc.  
KSZ8041NL  
Type(1)  
Ipd/O  
Pin Number  
Pin Name  
Pin Function  
20  
RXER /  
RX_ER /  
ISO  
MII Mode:  
Receive Error Output /  
Receive Error Output /  
RMII Mode:  
Config Mode:  
The pull-up/pull-down value is latched as ISOLATE during  
power-up / reset. See “Strapping Options” section for details.  
21  
INTRP  
Opu  
Interrupt Output: Programmable Interrupt Output  
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt  
conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt  
output to active low (default) or active high.  
22  
23  
TXC  
O
I
MII Mode:  
MII Mode:  
RMII Mode:  
Transmit Clock Output  
Transmit Enable Input /  
Transmit Enable Input  
TXEN /  
TX_EN  
TXD0 /  
TXD[0]  
MII Mode:  
RMII Mode:  
MII Mode:  
RMII Mode:  
MII Mode:  
Transmit Data Input[0](4)  
Transmit Data Input[0](5)  
Transmit Data Input[1](4)  
Transmit Data Input[1](5)  
Transmit Data Input[2](4)  
Transmit Data Input[3](4)  
Collision Detect Output /  
/
/
24  
25  
I
I
TXD1 /  
TXD[1]  
26  
27  
28  
TXD2  
TXD3  
I
/
/
I
MII Mode:  
COL /  
Ipd/O  
MII Mode:  
CONFIG0  
Config Mode:  
The pull-up/pull-down value is latched as CONFIG0 during  
power-up / reset. See “Strapping Options” section for details.  
29  
30  
CRS /  
Ipd/O  
Ipu/O  
MII Mode:  
Carrier Sense Output /  
CONFIG1  
Config Mode:  
The pull-up/pull-down value is latched as CONFIG1 during  
power-up / reset. See “Strapping Options” section for details.  
LED0 /  
LED Output:  
Config Mode:  
Programmable LED0 Output /  
NWAYEN  
Latched as Auto-Negotiation Enable (register 0h, bit 12) during  
power-up / reset. See “Strapping Options” section for details.  
The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as  
follows.  
LED mode = [00]  
Link/Activity  
No Link  
Link  
Pin State  
LED Definition  
OFF  
H
L
ON  
Activity  
Toggle  
Blinking  
LED mode = [01]  
Link  
Pin State  
LED Definition  
No Link  
Link  
H
L
OFF  
ON  
LED mode = [10]  
Reserved  
LED mode = [11]  
Reserved  
July 2008  
10  
M9999-071808-1.2