ENC28J60
Pointers will not be modified and no memory will be
written to. The EDMACSH and EDMACSL registers will
contain the calculated checksum. The host controller
may write this value into a packet, compare this value
with a received checksum, or use it for other purposes.
13.2 Checksum Calculations
The checksum calculation logic treats the source data as
a series of 16-bit big-endian integers. If the source range
contains an odd number of bytes, a padding byte of 00h
is effectively added to the end of the series for purposes
of calculating the checksum. The calculated checksum
is the 16-bit one’s complement of the one’s complement
sum of all 16-bit integers. For example, if the bytes
included in the checksum were {89h, ABh, CDh}, the
checksum would begin by computing 89ABh + CD00h.
A carry out of the 16th bit would occur in the example, so
in 16-bit one’s complement arithmetic, it would be added
back to the first bit. The resulting value of 56ACh would
finally be complemented to achieve a checksum of
A953h.
Various protocols, such as TCP and IP, have a checksum
field inside a range of data which the checksum covers.
If such a packet is received and the host controller needs
to validate the checksum, it can do the following:
1. Read the checksum from the packet and save it
to a temporary location
2. Write zeros to the checksum field.
3. Calculate a new checksum using the DMA
controller.
4. Compare the results with the saved checksum
from step 1.
To calculate a checksum:
1. Program the EDMAST and EDMAND register
pairs to point to the first and last bytes of buffer
data to be included in the checksum. Care should
be taken when programming these Pointers to
prevent a never ending checksum calculation
due to receive buffer wrapping.
Writing to the receive buffer is permitted when the write
address is protected by means of the ERXRDPT
Pointers. See Section 7.2 “Receiving Packets” for
additional information.
The IP checksum has unique mathematical properties
which may be used in some cases to reduce the
processing requirements further. Writing to the receive
buffer may be unnecessary in some applications.
2. To generate an optional interrupt when the
checksum calculation is done, clear EIR.DMAIF,
set EIE.DMAIE and set EIE.INTIE.
When operating the DMA in Checksum mode, it will
take one main clock cycle for every byte included in the
checksum. As a result, if a checksum over 1446 bytes
were performed, the DMA module would require
slightly more than 57.84 μs to complete the operation.
3. Start the calculation by setting ECON1.CSUMEN
and ECON1.DMAST.
When the checksum is finished being calculated, the
hardware will clear the DMAST bit, set the DMAIF bit
and an interrupt will be generated if enabled. The DMA
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER
Register
Reset
Values
on page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
EIE
INTIE
—
PKTIE
PKTIF
DMAIE
DMAIF
LINKIE
LINKIF
TXIE
TXIF
r
r
TXERIE RXERIE
13
13
13
13
13
EIR
TXERIF
BSEL1
RXERIF
BSEL0
ECON1
ERXNDL
ERXNDH
TXRST
RXRST
DMAST CSUMEN TXRTS
RXEN
RX End Low Byte (ERXND<7:0>)
—
—
—
RX End High Byte (ERXND<12:8>)
EDMASTL DMA Start Low Byte (EDMAST<7:0>)
EDMASTH
EDMANDL DMA End Low Byte (EDMAND<7:0>)
EDMANDH
13
13
13
13
13
13
13
—
—
—
DMA Start High Byte (EDMAST<12:8>)
—
—
—
DMA End High Byte (EDMAND<12:8>)
EDMADSTL DMA Destination Low Byte (EDMADST<7:0>)
EDMADSTH DMA Destination High Byte (EDMADST<12:8>)
—
—
—
EDMACSL DMA Checksum Low Byte (EDMACS<7:0>)
EDMACSH DMA Checksum High Byte (EDMACS<15:8>)
13
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the DMA controller.
DS39662B-page 72
Preliminary
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
