ENC28J60
TABLE 10-1: SUMMARY OF REGISTERS USED WITH FLOW CONTROL
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
ECON1
TXRST
—
RXRST
—
DMAST
—
CSUMEN
r
TXRTS
RXEN
BSEL1
BSEL0
13
14
14
14
14
14
MACON1
MABBIPG
EFLOCON
EPAUSL
EPAUSH
TXPAUS RXPAUS PASSALL MARXEN
—
Back-to-Back Inter-Packet Gap (BBIPG<6:0>)
—
—
—
—
—
FULDPXS FCEN1
FCEN0
Pause Timer Value Low Byte (EPAUS<7:0>)
Pause Timer Value High Byte (EPAUS<15:8>)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used.
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 57