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    ENC28J60-I/ML 参数 Datasheet PDF下载

    ENC28J60-I/ML图片预览
    型号： ENC28J60-I/ML
    PDF下载： 下载PDF文件 查看货源
    内容描述： 独立以太网控制器，SPI接口 [Stand-Alone Ethernet Controller with SPI Interface]
    分类和应用： 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输PC局域网以太网时钟
    文件页数/大小： 96 页 / 1466 K
    品牌： MICROCHIP [ MICROCHIP TECHNOLOGY ]
     浏览型号ENC28J60-I/ML的Datasheet PDF文件第87页浏览型号ENC28J60-I/ML的Datasheet PDF文件第88页浏览型号ENC28J60-I/ML的Datasheet PDF文件第89页浏览型号ENC28J60-I/ML的Datasheet PDF文件第90页浏览型号ENC28J60-I/ML的Datasheet PDF文件第92页浏览型号ENC28J60-I/ML的Datasheet PDF文件第93页浏览型号ENC28J60-I/ML的Datasheet PDF文件第94页浏览型号ENC28J60-I/ML的Datasheet PDF文件第95页  
    ENC28J60
    INDEX
    B
    Block Diagrams
    Crystal Oscillator Operation .......................................... 5
    ENC28J60 Architecture ................................................ 3
    Ethernet Buffer Organization ...................................... 18
    External Clock Source .................................................. 5
    External Connections.................................................... 7
    I/O Level Shifting
    3-State Buffers ...................................................... 8
    AND Gate ............................................................. 8
    Interrupt Logic ............................................................. 63
    LEDB Polarity Configuration ......................................... 8
    Memory Organization.................................................. 11
    On-Chip Reset Circuit ................................................. 59
    Typical Interface............................................................ 4
    Broadcast Filter ................................................................... 52
    Built-in Self-Test Controller ................................................. 75
    Address Fill Mode ....................................................... 76
    Associated Registers .................................................. 77
    EBSTCS registers....................................................... 76
    EBSTSD Register ....................................................... 76
    Pattern Shift Fill Mode................................................. 76
    Random Data Fill Mode .............................................. 76
    Use.............................................................................. 76
    Ethernet Overview .............................................................. 31
    External Connections (Diagram)........................................... 7
    F
    Filtering
    Using AND Logic ........................................................ 50
    Using OR Logic .......................................................... 49
    Flow Control........................................................................ 55
    Associated Registers.................................................. 57
    Full-Duplex Mode ....................................................... 55
    Half-Duplex Mode....................................................... 55
    Sample Full-Duplex Network (Diagram) ..................... 55
    Full-Duplex-Mode
    Operation.................................................................... 53
    H
    Half-Duplex-Mode
    Operation.................................................................... 53
    Hash Table Filter ................................................................ 52
    I
    I/O Level Shifting .................................................................. 8
    Using 3-State Buffers ................................................... 8
    Using AND Gates ......................................................... 8
    Initialization ......................................................................... 33
    MAC Settings.............................................................. 34
    PHY Settings .............................................................. 37
    Receive Buffer ............................................................ 33
    Receive Filters............................................................ 33
    Transmit Buffer ........................................................... 33
    Waiting for OST .......................................................... 33
    Interrupts ............................................................................ 63
    DMA Flag (DMAIF) ..................................................... 69
    INT Enable (INTIE) ..................................................... 64
    Link Change Flag (LINKIF)......................................... 69
    Receive Error Flag (RXERIF) ..................................... 68
    Receive Packet Pending Flag (PKTIF) ....................... 69
    Transmit Error Flag (TXERIF) .................................... 68
    Transmit Interrupt Flag (TXIF) .................................... 68
    C
    Checksum Calculations ...................................................... 72
    CLKOUT Pin ......................................................................... 6
    Control Register Map .......................................................... 12
    Control Register Summary............................................ 13–14
    Control Registers ................................................................ 12
    Customer Change Notification Service ............................... 91
    Customer Notification Service............................................. 91
    Customer Support ............................................................... 91
    D
    DMA Controller ................................................................... 71
    Access to Buffers ........................................................ 17
    Associated Registers .................................................. 72
    Checksum Calculations .............................................. 72
    Copying Memory......................................................... 71
    Duplex-Mode
    Configuration and Negotiation .................................... 53
    L
    LED Configuration ................................................................ 8
    LEDB Polarity and Reset Configuration................................ 8
    E
    Electrical Characteristics..................................................... 79
    Absolute Maximum Ratings ........................................ 79
    AC Characteristics ...................................................... 81
    CLKOUT Pin AC ......................................................... 81
    DC Characteristics ...................................................... 80
    Oscillator Timing ......................................................... 81
    Requirements for External Magnetics......................... 81
    Reset AC..................................................................... 81
    SPI Interface AC ......................................................... 82
    ENC28J60 Block Diagram .................................................... 3
    EREVID Register ................................................................ 22
    Errata .................................................................................... 2
    Ethernet Buffer .................................................................... 17
    Organization (Diagram)............................................... 18
    Ethernet Module
    Transmitting and Receiving Data
    Receive Packet Layout ....................................... 43
    Transmit Packet Layout ...................................... 40
    M
    Magic Packet Filter ............................................................. 52
    Magnetics and External Components................................... 7
    Memory Organization ......................................................... 11
    Multicast Filter..................................................................... 52
    O
    Oscillator............................................................................... 5
    CLKOUT Transition ...................................................... 6
    Crystal Oscillator .......................................................... 5
    External Clock Source .................................................. 5
    Start-up Timer............................................................... 5
    P
    Packaging Information ........................................................ 83
    Details......................................................................... 84
    Marking....................................................................... 83
    ©
    2006 Microchip Technology Inc.
    Preliminary
    DS39662B-page 89

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