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ENC28J60-I/ML 参数 Datasheet PDF下载

ENC28J60-I/ML图片预览
型号: ENC28J60-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 独立以太网控制器,SPI接口 [Stand-Alone Ethernet Controller with SPI Interface]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输PC局域网以太网时钟
文件页数/大小: 96 页 / 1466 K
品牌: MICROCHIP [ MICROCHIP ]
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ENC28J60  
If using half duplex, the host controller may wish to set  
the PHCON2.HDLDIS bit to prevent automatic  
loopback of the data which is transmitted.  
6.6  
PHY Initialization Settings  
Depending on the application, bits in three of the PHY  
module’s registers may also require configuration.  
The PHY register, PHLCON, controls the outputs of  
LEDA and LEDB. If an application requires a LED  
configuration other than the default, PHLCON must be  
altered to match the new requirements. The settings for  
LED operation are discussed in Section 2.6 “LED  
Configuration”. The PHLCON register is shown in  
Register 2-2 (page 9).  
The PHCON1.PDPXMD bit partially controls the  
device’s half/full-duplex configuration. Normally, this bit  
is initialized correctly by the external circuitry (see  
Section 2.6 “LED Configuration”). If the external  
circuitry is not present or incorrect, however, the host  
controller must program the bit properly. Alternatively,  
for an externally configurable system, the PDPXMD bit  
may be read and the FULDPX bit be programmed to  
match.  
For proper duplex operation, the PHCON1.PDPXMD  
bit must also match the value of the MACON3.FULDPX  
bit.  
REGISTER 6-5:  
PHCON2: PHY CONTROL REGISTER 2  
U-0  
R/W-0  
R/W-0  
TXDIS  
R/W-0  
r
R/W-0  
r
R/W-0  
R/W-0  
r
R/W-0  
FRCLNK  
JABBER  
HDLDIS  
bit 15  
bit 8  
R/W-0  
r
R/W-0  
r
R/W-0  
r
R/W-0  
r
R/W-0  
r
R/W-0  
r
R/W-0  
r
R/W-0  
r
bit 7  
bit 0  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
-n = Value at POR  
bit 15  
bit 14  
Unimplemented: Read as ‘0’  
FRCLNK: PHY Force Linkup bit  
1= Force linkup even when no link partner is detected  
0= Normal operation  
bit 13  
TXDIS: Twisted-Pair Transmitter Disable bit  
1= Disable twisted-pair transmitter  
0= Normal operation  
bit 12-11  
bit 10  
Reserved: Write as ‘0’  
JABBER: Jabber Correction Disable bit  
1= Disable jabber correction  
0= Normal operation  
bit 9  
bit 8  
Reserved: Write as ‘0’  
HDLDIS: PHY Half-Duplex Loopback Disable bit  
When PHCON1<8> = 1or PHCON1<14> = 1:  
This bit is ignored.  
When PHCON1<8> = 0and PHCON1<14> = 0:  
1= Transmitted data will only be sent out on the twisted-pair interface  
0= Transmitted data will be looped back to the MAC and sent out on the twisted-pair interface  
bit 7-0  
Reserved: Write as ‘0’  
© 2006 Microchip Technology Inc.  
Preliminary  
DS39662B-page 37