dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
8.0
AC/DC CHARACTERISTICS
AND TIMING REQUIREMENTS
Table 8-1 lists AC/DC characteristics and timing
requirements.
TABLE 8-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: –40°C-85°C. Programming at 25°C is recommended.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
(1)
D111 VDD
D112 IPP
D113 IDDP
D031 VIL
D041 VIH
D080 VOL
D090 VOH
D012 CIO
D013 CF
Supply Voltage During Programming
Programming Current on MCLR
Supply Current During Programming
Input Low Voltage
VDDCORE
3.60
5
V
μA
mA
V
Normal programming
—
—
2
VSS
0.8 VDD
—
0.2 VDD
VDD
0.6
—
Input High Voltage
V
Output Low Voltage
V
IOL = 8.5 mA @ 3.6V
IOH = -3.0 mA @ 3.6V
Output High Voltage
VDD – 0.7
—
V
Capacitive Loading on I/O pin (PGD)
Filter Capacitor Value on VCAP
Serial Clock (PGC) Period
50
pF To meet AC specifications
1
10
μF Required for controller core
P1
TPGC
136
40
—
ns
ns
ns
ns
ns
ns
P1A
P1B
P2
TPGCL
TPGCH
TSET1
THLD1
TDLY1
Serial Clock (PGC) Low Time
Serial Clock (PGC) High Time
Input Data Setup Time to Serial Clock ↓
Input Data Hold Time from PGC ↓
—
40
—
15
—
P3
15
—
P4
Delay between 4-bit Command and
Command Operand
40
—
P4A
P5
TDLY1A Delay between Command Operand and
Next 4-bit Command
40
20
—
—
ns
ns
TDLY2
Delay between Last PGC ↓ of Command
to First PGC ↑ of Read of Data Word
P6
P7
P8
TSET2
THLD2
TDLY3
VDD ↑ Setup Time to MCLR ↑
100
25
—
—
—
ns
ms
μs
Input Data Hold Time from MCLR ↑
Delay between Last PGC ↓ of Command
Byte to PGD ↑ by Programming Executive
12
P9a
P9b
TDLY4
TDLY5
Programming Executive Command
Processing Time
10
15
—
μs
μs
Delay between PGD ↓ by Programming
Executive to PGD Released by
Programming Executive
23
P10
P11
P12
P13
P14
P15
P16
P17
TDLY6
TDLY7
TDLY8
TDLY9
TR
PGC Low Time After Programming
Bulk Erase Time
400
200
20
1.5
—
—
—
ns
ms
ms
ms
μs
ns
s
Page Erase Time
—
Row Programming Time
MCLR Rise Time to Enter ICSP mode
Data Out Valid from PGC ↑
—
1.0
—
TVALID
10
0
TDLY10 Delay between Last PGC ↓ and MCLR ↓
THLD3 MCLR ↓ to VDD ↓
—
—
100
ns
Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be
within ±0.3V of VDD and VSS, respectively.
DS70152D-page 74
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
