Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
s
Arithmetic Shift Right
Swap Nibbles
Rd(n) Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)
None
Flag Set
SREG(s) 1
SREG(s) 0
T Rr(b)
Rd(b) T
C 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C 0
Set Negative Flag
N 1
Clear Negative Flag
Set Zero Flag
N 0
Z 1
Clear Zero Flag
Z 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I 1
I
CLI
I 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S 1
S
S
V
V
T
S 0
V 1
V 0
T 1
Clear T in SREG
T 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H 1
H
H
H 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd Rr+1:Rr
Load Immediate
Rd K
Rd, X
Load Indirect
Rd (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd (X), X X + 1
X X - 1, Rd (X)
Rd (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd (Y), Y Y + 1
Y Y - 1, Rd (Y)
Rd (Y + q)
Rd (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd (Z), Z Z+1
Z Z - 1, Rd (Z)
Rd (Z + q)
Rd (k)
LD
LDD
LDS
ST
X, Rr
(X) Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) Rr, X X + 1
X X - 1, (X) Rr
(Y) Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) Rr, Y Y + 1
Y Y - 1, (Y) Rr
(Y + q) Rr
ST
STD
ST
(Z) Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) Rr, Z Z + 1
Z Z - 1, (Z) Rr
(Z + q) Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) Rr
R0 (Z)
Rd, Z
Rd (Z)
Rd, Z+
Rd (Z), Z Z+1
(Z) R1:R0
Rd, P
P, Rr
Rr
Rd P
1
1
2
2
OUT
PUSH
POP
Out Port
P Rr
Push Register on Stack
Pop Register from Stack
STACK Rr
Rd STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
10
ATtiny2313
2543MS–AVR–10/16
MICROCHIP [ MICROCHIP ]
