ATmega48/88/168
Table 10-7 and Table 10-8 relate the alternate functions of Port C to the overriding signals
shown in Figure 10-5 on page 69.
Table 10-7. Overriding Signals for Alternate Functions in PC6..PC4(1)
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PC6/RESET/PCINT14
PC5/SCL/ADC5/PCINT13
PC4/SDA/ADC4/PCINT12
RSTDISBL
TWEN
TWEN
1
PORTC5 • PUD
TWEN
PORTC4 • PUD
TWEN
RSTDISBL
0
0
0
SCL_OUT
TWEN
SDA_OUT
TWEN
0
0
RSTDISBL + PCINT14 •
PCIE1
DIEOE
PCINT13 • PCIE1 + ADC5D
PCINT12 • PCIE1 + ADC4D
DIEOV
DI
RSTDISBL
PCINT13 • PCIE1
PCINT12 • PCIE1
PCINT14 INPUT
RESET INPUT
PCINT13 INPUT
PCINT12 INPUT
AIO
ADC5 INPUT / SCL INPUT
ADC4 INPUT / SDA INPUT
Note:
1. When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4
and PC5. This is not shown in the figure. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
Table 10-8. Overriding Signals for Alternate Functions in PC3..PC0
Signal
Name
PC3/ADC3/
PCINT11
PC2/ADC2/
PCINT10
PC1/ADC1/
PCINT9
PC0/ADC0/
PCINT8
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCINT11 • PCIE1 +
ADC3D
PCINT10 • PCIE1 +
ADC2D
PCINT9 • PCIE1 +
ADC1D
PCINT8 • PCIE1 +
ADC0D
DIEOE
DIEOV
DI
PCINT11 • PCIE1
PCINT11 INPUT
ADC3 INPUT
PCINT10 • PCIE1
PCINT10 INPUT
ADC2 INPUT
PCINT9 • PCIE1
PCINT9 INPUT
ADC1 INPUT
PCINT8 • PCIE1
PCINT8 INPUT
ADC0 INPUT
AIO
77
2545E–AVR–02/05