Table 6-13. Start-up Times for the External Clock Selection
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset (VCC = 5.0V)
Power Conditions
BOD enabled
SUT1..0
00
6 CK
6 CK
14CK
Fast rising power
14CK + 4.1 ms
14CK + 65 ms
01
Slowly rising power
6 CK
10
Reserved
11
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2ꢀ from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2ꢀ is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page
34 for details.
6.9
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
6.10 Timer/Counter Oscillator
The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-
nal clock source. The Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with
XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when an
internal RC Oscillator is selected as system clock source. See Figure 6-2 on page 28 for crystal
connection.
Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to
logic one. See ”Asynchronous operation of the Timer/Counter” on page 155 for further descrip-
tion on selecting external clock as input instead of a 32 kHz crystal.
6.11 System Clock Prescaler
The ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by
setting the ”Clock Prescale Register – CLKPR” on page 357. This feature can be used to
decrease the system clock frequency and the power consumption when the requirement for pro-
cessing power is low. This can be used with all clock source options, and it will affect the clock
frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are
divided by a factor as shown in Table 8-1 on page 44.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
34
ATmega48/88/168
2545E–AVR–02/05
MICROCHIP [ MICROCHIP ]
