欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48V-10MUR 参数 Datasheet PDF下载

ATMEGA48V-10MUR图片预览
型号: ATMEGA48V-10MUR
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 4KB FLASH 32VQFN]
分类和应用: 时钟微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第19页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第20页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第21页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第22页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第24页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第25页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第26页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第27页  
ATmega48/88/168  
The next code examples show assembly and C functions for reading the EEPROM. The exam-  
ples assume that interrupts are controlled so that no interrupts will occur during execution of  
these functions.  
Assembly Code Example  
EEPROM_read:  
; Wait for completion of previous write  
sbic EECR,EEPE  
rjmp EEPROM_read  
; Set up address (r18:r17) in address register  
out EEARH, r18  
out EEARL, r17  
; Start eeprom read by writing EERE  
sbi EECR,EERE  
; Read data from Data Register  
in r16,EEDR  
ret  
C Code Example  
unsigned char EEPROM_read(unsigned int uiAddress)  
{
/* Wait for completion of previous write */  
while(EECR & (1<<EEPE))  
;
/* Set up address register */  
EEAR = uiAddress;  
/* Start eeprom read by writing EERE */  
EECR |= (1<<EERE);  
/* Return data from Data Register */  
return EEDR;  
}
5.3.5  
Preventing EEPROM Corruption  
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is  
too low for the CPU and the EEPROM to operate properly. These issues are the same as for  
board level systems using EEPROM, and the same design solutions should be applied.  
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,  
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-  
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.  
EEPROM data corruption can easily be avoided by following this design recommendation:  
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can  
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal  
BOD does not match the needed detection level, an external low VCC reset Protection circuit can  
be used. If a reset occurs while a write operation is in progress, the write operation will be com-  
pleted provided that the power supply voltage is sufficient.  
23  
2545E–AVR–02/05  
 复制成功!