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ATMEGA48V-10MUR 参数 Datasheet PDF下载

ATMEGA48V-10MUR图片预览
型号: ATMEGA48V-10MUR
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 4KB FLASH 32VQFN]
分类和应用: 时钟微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
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ATmega48/88/168  
Assembly Code Examples(1)  
...  
; Set TCNT1 to 0x01FF  
ldir17,0x01  
ldir16,0xFF  
outTCNT1H,r17  
outTCNT1L,r16  
; Read TCNT1 into r17:r16  
in r16,TCNT1L  
in r17,TCNT1H  
...  
C Code Examples(1)  
unsigned int i;  
...  
/* Set TCNT1 to 0x01FF */  
TCNT1 = 0x1FF;  
/* Read TCNT1 into i */  
i = TCNT1;  
...  
Note:  
1. See ”About Code Examples” on page 6.  
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”  
instructions must be replaced with instructions that allow access to extended I/O. Typically  
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.  
The assembly code example returns the TCNT1 value in the r17:r16 register pair.  
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt  
occurs between the two instructions accessing the 16-bit register, and the interrupt code  
updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-  
ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both  
the main code and the interrupt code update the temporary register, the main code must disable  
the interrupts during the 16-bit access.  
The following code examples show how to do an atomic read of the TCNT1 Register contents.  
Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.  
109  
2545E–AVR–02/05  
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