ATmega48/88/168
Table 18-1. Equations for Calculating Baud Rate Register Setting
Equation for Calculating Baud
Rate(1)
Equation for Calculating UBRRn
Value
Operating Mode
Synchronous Master
mode
f
OSC
f
OSC
BAUD = --------------------------------------
UBRRn = -------------------- – 1
2(UBRRn + 1)
2BAUD
Note:
1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
Baud rate (in bits per second, bps)
fOSC
System Oscillator clock frequency
UBRRn
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
18.3 SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in Figure 18-1. Data bits are shifted out and latched in on opposite edges of the XCKn
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in Table 18-2. Note that changing the setting of any of these bits will corrupt
all ongoing communication for both the Receiver and Transmitter.
Table 18-2. UCPOLn and UCPHAn Functionality-
UCPOLn
UCPHAn
SPI Mode
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
0
0
1
1
0
1
0
1
0
1
2
3
Figure 18-1. UCPHAn and UCPOLn data transfer timing diagrams.
UCPOL=0
UCPOL=1
XCK
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
197
2545E–AVR–02/05
MICROCHIP [ MICROCHIP ]
