ATmega48/88/168
16. Serial Peripheral Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega48/88/168 and peripheral devices or between several AVR devices. The
ATmega48/88/168 SPI includes the following features:
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 196. The
PRSPI bit in ”Power Reduction Register - PRR” on page 40 must be written to zero to enable
SPI module.
Figure 16-1. SPI Block Diagram(1)
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Note:
1. Refer to Figure 1-1 on page 2, and Table 10-3 on page 71 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 16-2. The sys-
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
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2545E–AVR–02/05
MICROCHIP [ MICROCHIP ]
