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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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Table 12-2. Compare Output Mode, non-PWM Mode  
COM0A1  
COM0A0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.  
Toggle OC0A on compare match  
Clear OC0A on compare match  
Set OC0A on compare match  
Table 12-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.  
Table 12-3. Compare Output Mode, Fast PWM Mode(1)  
COM0A1  
COM0A0  
Description  
0
0
Normal port operation, OC0A disconnected.  
WGM02 = 0: Normal port operation, OC0A disconnected.  
WGM02 = 1: Toggle OC0A on compare match.  
0
1
1
1
0
1
Clear OC0A on compare match, set OC0A at TOP  
Set OC0A on compare match, clear OC0A at TOP  
Note:  
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is  
ignored, but the set or clear is done at TOP. See Section 12.6.3 “Fast PWM Mode” on page 83 for more details.  
Table 12-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.  
Table 12-4. Compare Output Mode, Phase Correct PWM Mode(1)  
COM0A1  
COM0A0  
Description  
0
0
Normal port operation, OC0A disconnected.  
WGM02 = 0: Normal port operation, OC0A cisconnected.  
WGM02 = 1: Toggle OC0A on compare match.  
0
1
1
1
0
1
Clear OC0A on compare match when up-counting. Set OC0A on compare match  
when down-counting.  
Set OC0A on compare match when up-counting. Clear OC0A on compare match  
when down-counting.  
Note:  
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is  
ignored, but the set or clear is done at TOP. See Section 13.8.4 “Phase Correct PWM Mode” on page 105 for  
more details.  
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode  
These bits control the output compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output  
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR)  
bit corresponding to the OC0B pin must be set in order to enable the output driver.  
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. Table 12-5  
shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).  
Table 12-5. Compare Output Mode, non-PWM Mode  
COM0B1  
COM0B0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC0B disconnected.  
Toggle OC0B on compare match  
Clear OC0B on compare match  
Set OC0B on compare match  
ATmega16/32/64/M1/C1 [DATASHEET]  
87  
7647O–AVR–01/15  
 
 
 
 
 
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