24.7.7 Setting the Boot Loader Lock Bits by SPM
To set the boot loader lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four
clock cycles after writing SPMCSR. The only accessible lock bits are the boot lock bits that may prevent the application and
boot loader section from any software update by the MCU.
Bit
7
6
5
4
3
2
1
0
R0
1
1
BLB12
BLB11
BLB02
BLB01
1
1
See Table 24-2 and Table 24-3 for how the different settings of the boot loader bits affect the flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding boot lock bit will be programmed if an SPM instruction is executed
within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for
future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the lOck bits). For future
compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When programming the
lock bits the entire flash can be read during the operation.
24.7.8 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to flash. Reading the fuses and lock bits from
software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit
(EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR register.
24.7.9 Reading the Fuse and Lock Bits from Software
It is possible to read both the fuse and lock bits from software. To read the lock bits, load the Z-pointer with 0x0001 and set
the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET
and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and
SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU
cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as
described in the instruction set manual.
Bit
Rd
7
6
5
4
3
2
1
0
–
–
BLB12
BLB11
BLB02
BLB01
LB2
LB1
The algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. To read the fuse
low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR.
When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
value of the fuse low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 25-4 on page 256
for a detailed description and mapping of the fuse low byte.
Bit
7
6
5
4
3
2
1
0
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the fuse high byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three
cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the fuse high byte (FHB) will be loaded in the
destination register as shown below. Refer to Table 25-6 on page 257 for detailed description and mapping of the fuse high
byte.
Bit
7
6
5
4
3
2
1
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
When reading the extended fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles
after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the extended fuse byte (EFB) will be loaded in the
destination register as shown below. Refer to Table 25-4 on page 256 for detailed description and mapping of the extended
fuse byte.
Bit
7
6
5
4
3
2
1
0
Rd
–
–
–
–
EFB3
EFB2
EFB1
EFB0
Fuse and lock bits that are programmed, will be read as zero. Fuse and lock bits that are unprogrammed, will be read as
one.
248
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
